Accelicon

DFM-Aware PDK QA Platform

Overview

Like for SPICE models, comprehensive QA and verification of the Process Design Kit (PDK) are also required in order to ensure design success. However, with DFM (Design For Manufacture) considerations, Process Design Kit (PDK) has become more and more complicated, more procedures and tools are involved and efforts of verification are tremendous without automation. Accelicon has developed an automated yet flexible solution for DFM-aware PDK verification by (1) integration of EDA tools needed for PDK verification. (2) A rule driven feature that ensures the flexibility. (3) Open interfaces ready to be adjusted to suit for any design flow or future challenges.

Introduction

The PQA platform consists all the blocks needed for PDK verifications including test structure generation, layout extraction, SPICE simulation and Data Analysis. The platform can be tuned for different applications. For example, Accelicon’s MQA is focused on the last two blocks, SPICE simulation and Data Analysis and if no simulation is needed, user can tune the platform for verifying the extraction decks. And normally for running PQA, we include all the four blocks and each block is independent of each other. The four blocks are:

Layout Generation Block – To generate the test structures DOE (Design of Experiments) automatically according to user specification.

Layout Extraction Block – To exact the generated layout into SPICE netlist, here, extraction decks can be decks with or without DFM implementation, with or without parasitic extraction.

SPICE Simulation Block – To plug in the SPICE model and call SPICE simulators to run simulation.

Data Analysis Block – To plot and analyze the data generated by the previous blocks.

All the blocks are driven by Rule files.
Rule file contains simple syntax that defines the following:
Design of Experiment (DOE) of the test bench.
"Path" to layout generator, foundry PCELL, standard cell or user layout.
SPICE Model
"Analyzed Target": Idsat, Vth for transistors and delay/slew for simple circuits.
"Action": "Comparison" or "Analysis functions" or "Analytical"

Layout Generator automatically generates test structure from:

Foundry PCELL
SKILL based layout generator
Existing or user layout

Layout Generator automatically generates test structure from:

Foundry PCELL
SKILL based layout generator
Existing or user layout

Device type, ports and targets are controlled by the ICF file.
PQA adopts a “Black Box” approach for defining circuits.
User is able to define targets and check functions.
This mechanism enables user to easily expand and customize what to see and what to check in PQA

Each block is independent from each other to improve efficiency.

The interface of each block is customizable.